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Nikhilendu Tiwary; Vesa Vuorinen; Glenn Ross; Mervi Paulasto-Kröckel: Finite Element Simulation of Solid–Liquid Interdiffusion Bonding Process: Understanding Process-Dependent Thermomechanical Stress
Published in: IEEE Transactions on Components, Packaging and Manufacturing Technology
Date Added to IEEE Xplore: 25 April 2022
INSPEC Accession Number: 21414908
DOI: 10.1109/TCPMT.2022.3170082
Publisher: IEEE
Abstract: Solid–liquid interdiffusion (SLID) bonding finds a wide variety of potential applications toward die-attach, hermetic encapsulation of microelectromechanical systems (MEMS) devices and 3-D heterogeneous integration. Unlike soft soldering technique, the solidification of intermetallic compound (IMC) formation in SLID bonding occurs during the process isothermally, making it difficult to predict and mitigate the sources of process-dependent thermomechanical stresses. Literature reports two dominant factors for the built-in stress in SLID bonds: volume shrinkage (due to IMC formation) and coefficient of thermal expansion (CTE) mismatch. This work provides a detailed investigation of the Cu–Sn SLID bonding process by finite element (FE) simulations. Specifically, the FE simulation of the SLID bonding process is divided into three steps: ramp-up, hold-time, and ramp-down stages to understand the stresses formed due to each individual step. Plastic material properties for Cu as well as temperature-dependent material parameters for different entities are assigned. Process-dependent thermomechanical stresses formed during the ramp-up and hold-time steps (IMC formation) were found not to be significant. The hold-time step is governed by the reaction and diffusion kinetics, which determines the bond line quality including defects, such as voids. The ramp-down step is the dominant phase influencing the final stress formations in the bonds. The results show an average of >30% decrease in the stress levels in Cu3Sn layer (IMC) when the bonding temperature is brought down from 320 °C to 200 °C, thus demonstrating the importance of low-temperature SLID process.
Obert Golim et al. : Low-temperature Metal Bonding for Optical Device Packaging
Published in: 2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)
Date of Conference: 13-16 Sept. 2021
Date Added to IEEE Xplore: 13th of November 2021
INSPEC Accession Number: 21414908
DOI: 10.23919/EMPC53418.2021.9585007
Publisher: IEEE
Abstract: Low-temperature solid-liquid interdiffusion (SLID) bonding is an attractive alternative for the packaging of optical devices. It reduces global residual stress build up caused by differences in coefficient of thermal expansion (CTE) at elevated temperatures. This work applied the Cu-Sn-In-based SLID bonding method to bond silicon and optically transparent materials at 200 °C. Experimental results show a successful bonding with minor unavoidable misalignment from the CTE mismatch and major misalignment from the bonding alignment process. Microstructural analysis shows the intermetallic compound consists only of Cu 6 (Sn,In) 5 on the bond that is thermally stable up to 600 °C.
Hexin Xia et al. : Impact of Micromachining Process on CU-Sn Solid-Liquid Interdiffusion (SLID) Bonds
Published in: 2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)
Date of Conference: 13-16 Sept. 2021
Date Added to IEEE Xplore: 13th of November 2021
INSPEC Accession Number: 21414884
DOI: 10.23919/EMPC53418.2021.9584992
Publisher: IEEE
Abstract: Copper-tin Solid-Liquid Interdiffusion (Cu-Sn SLID) bonding has shown potential for packaging of microelectromechanical system (MEMS) devices such as microbolometers due to its low cost and high-temperature stability. A thin micromachined silicon cap is desired in the packaging of microbolometers to minimize the infrared light absorption. In the preferred fabrication process flow, the Cu-Sn sealing frames are deposited on both the cap and device wafers prior to micromachining the cap wafer. This method greatly simplifies the process compared to when the metal layers are deposited after the cap etching process. However, such an approach might affect the bonding quality due to the Cu-Sn sealing frame being used directly as a mask for the cap etching. The present work addresses this concern using a cap wafer (with and without micromachining process) bonded to a device wafer using the Cu-Sn SLID technique. A dicing yield at or near 100% is achieved for both samples. The interface of Cu-Sn bonds shows a similar Cu/Cu 3 Sn/Cu structure between the samples without cavity and with a cavity, which indicates that the micromachining process has a minor impact on the Cu-Sn bonds. However, the measured die shear strengths of the samples with and without cavity are relatively low due to fracture at the Cu/Cu 3 Sn interface and adhesion fracture at the TiW layer. The bond strength can be further improved by optimizing the Cu/Sn electroplating process and improving the adhesion layer.
Phillip Papatzacos et al. : Investigation of seal frame geometry of Sn squeeze-out in Cu-Sn SLID bonds
Published in: 2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)
Date of Conference: 13-16 Sept. 2021
Date Added to IEEE Xplore: 12th of November 2021
INSPEC Accession Number: 21414878
DOI: 10.23919/EMPC53418.2021.9584990
Publisher: IEEE
Abstract: Cu-Sn SLID is an increasingly popular bonding technique with applications in such as hermetic sealing of microbolometers. A moderate bonding pressure is necessary to compensate for the surface roughness of the electroplated layers and to break the Sn oxide layer, thereby reducing the risk of voiding. However, such bonding pressures increase the risk for Sn squeeze-out during the bonding process, which has the potential to destroy MEMS or ROIC devices. To prevent this potential issue, an alternative bondline geometry consisting of 3×50µm wide bond rails and 25µm wide gaps was manufactured and compared to a continuous 200µm bondline by using nondestructive IR imaging, cross-sectional microscopy, and die-shear testing. High shear strength values of 31±9MPa and 43±18MPa were obtained for continuous and railed seal frames respectively. The Sn squeeze-out distance beyond the intended bondline was, on average, reduced by 60% when the railed geometry is employed. A reduction in peak squeeze-out distance from 188µm to 54µm was also observed.
Hexin Xia et al. : Design of Silicon Cap for Hermetic Packaging of Microbolometer Focal Plane Arrays
Published in: IEEE Transactions on Components, Packaging and Manufacturing Technology (Volume: 12, Issue: 3, March 2022)
DOI: 10.1109/TCPMT.2021.3135081
Publisher: IEEE
Abstract: A microbolometer array (MBA) is used as a detector in an infrared (IR) camera. It converts the temperature change induced by the incoming longwave IR (LWIR) light into an electrical signal for obtaining the thermal image information. The MBA must be hermetically packaged to maintain the necessary performance and long lifetime. Cavities are often micromachined on single-crystal silicon (SCS) cap wafers for the encapsulation of the sensor, where an increased cavity volume facilitates maintaining the vacuum level. The resulting thin cap is suitable for high transmission of IR signals. However, a thinner cap causes a larger deflection after hermetic packaging because of the pressure difference between the atmosphere and the vacuum inside the package. Large cap deflection can affect focus of the IR light on the MBA, while thinner caps are also prone to fracture. This article investigates the mechanical behavior and optical performance of silicon (Si) cap as a function of its thickness in the range 60– 300μm , for size 8 mm ×8 mm, 10 mm ×10 mm, and 12 mm ×12 mm using COMSOL and Zemax software. The leak rate necessary to fulfill the lifetime requirements of the MBAs is also discussed. The mechanical simulations indicate that mechanical failure will occur for a cap thinner than 70μm with a chip size of 10 mm ×10 mm, and 90μm with a chip size of 12 mm ×12 mm. No failure is observed for a chip size of 8 mm ×8 mm with a cap thickness in the range of 60– 300μm . The optical simulation results reveal that the increased deflection of the thinner caps has a negligible impact on the IR light focusing.
Birgit Brandstätter et al. : High-speed ultra-accurate direct C2W bonding
Published in: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
Date of Conference: 3-30 June 2020
Date Added to IEEE Xplore: 05 August 2020
INSPEC Accession Number: 19889569
DOI: 10.1109/ECTC32862.2020.00303
Publisher: IEEE
Abstract: Chip-to-wafer hybrid bonding is needed as contact pitch and pad size decrease to the single micrometer range (5 micrometer or lower). Here, classical bonding technologies like themo-compression bonding and flip-chip with mass reflow are no longer sufficient, and hybrid bonding emerges as an attractive alternative. While the technology is well known in wafer-to-wafer processing, for chip-to-wafer at industrial speed and accuracy, new placement technologies and deeper understanding of accuracy behavior during the bonding process both are essential. This paper describes new optical recognition methods for small pads for accurate in-situ alignment before the bonding stroke as well as a new bond-head design and behavior for accurate placement at 200 nm at each point of the die, including large dies, and at speeds of 2000 units per hour.
Also available at: Besi.com scientific publications
Joseph Hotchkiss; Vesa Vuorinen; Hongqun Dong; Glenn Ross; Jani Kaaos; Mervi Paulasto-Kröckel; Tobias Wernicke; Anneliese Pönninger : Study of Cu-Sn-In System for Low Temperature, Wafer Level Solid Liquid Inter-Diffusion Bonding
Published in: 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)
Date of Conference: 15-18 Sept. 2020
Date Added to IEEE Xplore: 23 October 2020
DOI: 10.1109/ESTC48849.2020.9229696
Publisher: IEEE
Abstract: The Solid Liquid Interdiffusion (SLID) bonds carried out for this work take advantage of the Cu-In-Sn ternary system to achieve low temperature wafer-level bonds. The experiments were carried out across a range of temperatures and the results cover optimized wafer-level bonding process, the formation of the bond microstructure, mechanical performance, as well as the effects of thermal aging.
Phillip Papatzacos; M. Nadeem Akram; Eivind Bardalen; Per Øhlckers : Simulated effects of wet-etched induced surface roughness on IR transmission and reflection
Published in: 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)
Date of Conference: 15-18 Sept. 2020
Date Added to IEEE Xplore: 23 October 2020
DOI: 10.1109/ESTC48849.2020.9229821
Publisher: IEEE
Abstract: We have constructed a finite element simulation where we investigate the effects of wet-etch-induced surface roughness on transmission and reflection of infrared light in the 8-12um band. A silicon wafer was wet-etched for 2 hours in a 10% KOH solution at 80°C, scanned in an atomic force microscope, and the surface profile was recreated in COMSOL. Simulated plane waves of light and varying angles of incidence were then allowed to pass through this surface and the resulting effects on the reflection and transmission were investigated. Roughness was then amplified to investigate the effects of increased surface roughness. For the wavelengths investigated, an increase in transmission of 8% could be seen up to an RMS surface roughness of 800nm followed by a decrease, while the angles investigated showed an RMS dependent increase in transmission between 20° and 40° for RMS surface roughness’ above 1000nm.
Hexin Xia; Muhammed Nadeem Akram; Eivind Bardalen; Avisek Roy; Knut Eilif Aasmundtveit; Per Ohlckers : Evaluation of Silicon Diaphragms for Hermetic Packaging of Microbolometer Arrays
Published in: 2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)
Date of Conference: 15-18 Sept. 2020
Date Added to IEEE Xplore: 23 October 2020
INSPEC Accession Number: 20066413
DOI: 10.1109/ESTC48849.2020.9229710
Publisher: IEEE
Abstract: Hermetic packaging is a critical requirement for microbolometers to maintain long-term reliability. A thinner diaphragm is desirable for vacuum packaging of microbolometers to obtain higher infrared light transmission. However, a thinner diaphragm results in a larger deflection due to the pressure difference from atmosphere, which may influence the IR signal focus and possibly cause mechanical failure. In this paper, the trade-offs of using thin single crystal silicon diaphragms as encapsulation for hermetic packaging of microbolometer arrays have been investigated in terms of the mechanical stability and optical performance using COMSOL and Zemax. The optical simulations show that the bending of the thin diaphragm has negligible effect on the infrared light focus with wavelengths from 8 to 14 μm. The mechanical simulations reveal that a thin diaphragm (thickness <; 70 μm) with 10×10 mm 2 area and a diaphragm (thickness <; 90 μm) with 12×12 mm 2 area will cause mechanical failure, and the designed diaphragm thickness must incorporate margins to these values.
Xing Dai; Hélène Debrégeas; Guillaume Da Rold; David Carrara; Kevin Louarn; Elena Durán Valdeiglesias; François Lelarge : Versatile Externally Modulated Lasers Technology for Multiple Telecommunication Applications
Published in: IEEE Journal of Selected Topics in Quantum Electronics ( Volume: 27, Issue: 3, May-June 2021)
Article Sequence Number: 3400412
Date of Publication: 07 October 2020
Publisher: IEEE
Abstract: This paper presents our technological approach for Externally Modulated Lasers (EMLs), based on Semi-Insulating Buried Heterostructure (SIBH) waveguide. We use Gas Source Molecular Beam Epitaxy (GSMBE) to grow the Phosphorus-based multi-quantum wells for both laser and modulator sections with butt-joint integration. The same GSMBE grows the p-doped InP claddings with low-diffusion Be dopant, leading to an accurate control of doping profiles, ensuring very steep modulator extinction curves. We present the main EML design rules and compromises, then apply them to different EMLs aiming at major telecom and datacom applications. After presenting characteristics of the standard 10 Gb/s C-band EML, we propose a 10 Gb/s EML at 1577 nm for next generation access networks, with a record high 10.5 dBm facet modulated power. Then we present high-speed EMLs up to 56 GBaud for datacenter interconnections, both in O- and C-band, aiming at very low peak-to-peak modulation voltage (< 1.2 V), high facet modulated power (> 4.4 dBm), and compatible with uncooled operation (20 to 70 °C). These results confirm the efficiency and versatility of this technological platform for EMLs in a broad range of applications.
Also available in TechRivx
V. Vuorinen, H. Dong, Glenn Ross, Joseph Hotskiss, J. Kaaos, Mervi Paulasto-Kröckel : Wafer Level SLID Bonding – Formation and Evolution of Microstructures
Presented at TMS 2020 Microelectronic Packaging, Interconnect, and Pb-free Solder: www.programmaster.org/PM/PM.nsf/ApprovedAbstracts/C5DB37F0B60B02FE852584270022B9D2?OpenDocument
Date of Conference: February 2020
DOI: https://doi.org/10.1007/s11664-020-08530-y
Abstract: Wafer-level solid liquid interdiffusion (SLID) bonding, also known as transient liquid-phase bonding, is becoming an increasingly attractive method for industrial usage since it can provide simultaneous formation of electrical interconnections and hermetic encapsulation for microelectromechanical systems. Additionally, SLID is utilized in die-attach bonding for electronic power components. In order to ensure the functionality and reliability of the devices, a fundamental understanding of the formation and evolution of interconnection microstructures, as well as global and local stresses, is of utmost importance. In this work a low-temperature Cu-In-Sn based SLID bonding process is presented. It was discovered that by introducing In to the traditional Cu-Sn metallurgy as an additional alloying element, it is possible to significantly decrease the bonding temperature. Decreasing the bonding temperature results in lower CTE induced global residual stresses. However, there are still several open issues to be studied regarding the effects of dissolved In on the physical properties of the Cu-Sn intermetallics. Additionally, partially metastable microstructures were observed in bonded samples that did not significantly evolve during thermal annealing. This indicates the Cu-In-Sn SLID bond microstructure is extremely stable.
Vesa Vuorinen, Glenn Ross, Anton Klami, Hongqun Dong, Mervi Paulasto-Kröckel, Tobias Wernicke, Anneliese Pönninger : Demonstrating 170°C Low Temperature Cu-In-Sn wafer level Solid Liquid Interdiffusion Bonding, IEEE Components, Packaging and Manufacturing Technology
Published in: IEEE Transactions on Components, Packaging and Manufacturing Technology
Date of Publication: 09 September 2021
DOI: 10.1109/TCPMT.2021.3111345
Publisher: IEEE
Abstract: The wafer-level Solid Liquid Interdiffusion (SLID) bonds carried out for this work take advantage of the Cu-In-Sn ternary system to achieve low temperature interconnections. The 100mm Si wafers had μ-bumps from 250μm down to 10μm fabricated by consecutive electrochemical deposition of Cu, Sn and In layers. The optimized wafer-level bonding processes were carried out by EV Group and Aalto University across a range of temperatures from 250°C down to 170°C. Even though some process quality related challenges were observed, it could be verified that high strength bonds with low defect content can be achieved even at a low bonding temperature of 170°C with an acceptable 1-hour wafer-level bonding duration. The microstructural analysis revealed that the bonding temperature significantly impacts the obtained phase structure as well as the number of defects. A higher (250°C) bonding temperature led to the formation of Cu3Sn phase in addition to Cu6(Sn,In)5 and resulted in several voids at Cu3Sn|Cu interface. On the other hand, with lower (200°C and 170°C) bonding temperatures the interconnection microstructure was composed purely of void free Cu6(Sn,In)5. The mechanical testing results revealed the clear impact of bonding quality on the interconnection strength.
